The invention pertains to etching processes and semiconductive material assemblies, and has particular application to capacitors and DRAMS, as well as to methods of forming capacitors and DRAMs.
Modern semiconductor device fabrication processes frequently utilize selective etching conditions during fabrication of semiconductor devices. Selective etching conditions will etch one material more rapidly than another. The material that is etched most rapidly can be referred to as a sacrificial material, and that which is etched less rapidly can be referred to as a protective (or etch stop) material. Selective etching can be utilized in, for example, processes in which it is desired to protect a portion of a semiconductive wafer from etching conditions while etching through another portion of the wafer. Example selective etching conditions are dry etch conditions selective for etching silicon oxide relative to silicon nitride. Such example selective etching conditions are described in U.S. Pat. No. 5,286,344, which is hereby incorporated by reference.
Many selective etching methods currently practiced generally have selectivities of about 10:1 or less. In other words, the etch conditions will selectively etch a first (sacrificial) material at a rate that is less than or equal to about twice as fast as that at which a second (protective) material is etched. At selectivities of 10:1 or less, there is a constant risk that the protective material will be etched entirely away s during the etching of the sacrificial material. Accordingly, it would be desirable to develop alternative methods of selective etching having selectivities of greater than 10:1.
A possible mechanism by which selectivity can occur is through selective polymer formation on the protective material during etching of it and the sacrificial material. For instance, etching of silicon oxide and silicon nitride under conditions such as those described in U.S. Pat. No. 5,286,344 may create a carbonaceous polymer on the silicon nitride which protects the silicon nitride during etching of the silicon oxide. The carbon contained in the carbonaceous polymer can originate from, for example, etchant materials (either gas, liquid or plasma materials), such as, for example, the CH2F2 and CHF3 described in U.S. Pat. No. 5,286,344. When silicon oxide, such as BPSG is selectively etched relative to silicon nitride, the carbon will frequently originate at least in part from etching of the BPSG. Thus, less selectivity is obtained when less BPSG is etched relative to an amount of silicon nitride exposed to the etching conditions. Accordingly, thin layers of BPSG can be more difficult to etch than thicker layers. Many selective etching methods are non-effective for selectively etching BPSG relative to silicon nitride when the BPSG layers have thicknesses of less than or equal to about 1.3 microns.
An exemplary application of selective etching is a dynamic random access memory (DRAM) forming process. Referring to FIG. 1, a DRAM construction is illustrated with respect to a semiconductive wafer fragment 10. Wafer fragment 10 comprises a substrate 12. Substrate 12 can be, for example, a monocrystalline wafer lightly doped with a p-type background dopant. To aid in interpretation of the claims that follow, the term xe2x80x9csemiconductive substratexe2x80x9d is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term xe2x80x9csubstratexe2x80x9d refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
Field oxide regions 15 overlie substrate 12, and node locations 14, 16, and 18 are between the field oxide regions. The node locations contain diffusion regions conductively doped with a conductivity-enhancing dopant.
Wordlines 20 and 22 overlie over substrate 12. Wordlines 20 and 22 comprise a gate oxide layer 24 and a conductive layer 26. Gate oxide layer 24 can comprise, for example, silicon dioxide. Conductive layer 26 can comprise, for example, conductively doped polysilicon capped with a metal silicide, such as, for example, tungsten silicide or titanium silicide. Wordlines 20 and 22 have opposing sidewall edges, and sidewall spacers 28 and 30 extend along such sidewall edges. An etch stop layer 32 extends over wordlines 20 and 22. Etch stop layer 32 can comprise, for example, silicon nitride. Although not shown, an insulative layer may be placed between etch stop layer 32 and conductive layer 26. Such insulative layer can comprise, for example, silicon oxide or silicon nitride.
An insulative layer 34 is provided over substrate 12 and over wordlines 20 and 22. Insulative layer 34 can comprise, for example, borophosphosilicate glass (BPSG).
Capacitor constructions 36 and 38 extend through insulative layer 34 to contact node locations 14 and 18, respectively. Capacitor constructions 36 and 38 comprise a storage node (first electrode) 40, a dielectric layer 42, and a second electrode 44. Storage node 40 and second electrode 44 can comprise, for example, conductively doped silicon such as conductively doped polysilicon. Dielectric layer 42 can comprise, for example, silicon dioxide and/or silicon nitride. Although all of layers 40, 42 and 44 are shown extending within openings in layer 34, it is noted that other capacitor constructions are known wherein some or none of the storage node, dielectric, and second electrode layers extend within an opening.
A bit line contact 46 also extends through insulative layer 34, and contacts node location 16. Bit line contact 46 is in gated electrical connection with capacitor construction 36 through wordline 20, and in gated electrical connection with capacitor 38 through wordline 22. Bit line contact 46 can comprise, for example, tungsten, titanium, and/or titanium nitride. Although not shown, a diffusion barrier layer, such as, for example, titanium nitride, can be formed between bit line contact 46 and the diffusion region of node location 16.
A second insulative layer 48 extends over capacitor constructions 36 and 38, and electrically isolates second electrodes 44 from bit line contact 46. Second insulative layer 48 can comprise the same material as first insulative layer 34. Second insulative layer 48 can comprise, for example, silicon dioxide, BPSG, or silicon nitride.
A bit line 50 extends over second insulative layer 48 and in electrical connection with bit line contact 46. Accordingly, bit line contact 46 electrically connects bit line 50 to node location 16. Bit line 50 can comprise, for example, aluminum, copper, or an alloy of aluminum and copper.
A method of forming the DRAM construction of FIG. 1 is described with reference to FIGS. 2-3. FIG. 2 illustrates semiconductive wafer fragment 10 at a preliminary processing step. Etch stop layer 32 extends over wordlines 20 and 22, and over node locations 14, 16 and 18. Insulative layer 34 extends over etch stop layer 32, and a patterned photoresist masking layer 60 is provided over insulative layer 34. Patterned photoresist layer 60 defines an opening 62 which is to be extended to node location 16 for ultimate formation of bit line contact 46 therein.
Referring to FIG. 3, opening 62 is extended to etch stop layer 32. The etch utilized to extend opening 62 is preferably selective for the material of layer 34 relative to that of layer 32. For instance, if layer 34 comprises BPSG and layer 32 comprises nitride, the etch can utilize a fluorocarbon material such as one or more of the materials disclosed in U.S. Pat. No. 5,286,344.
After selectively etching to layer 32, subsequent anisotropic etching of layer 32 can occur to extend opening 62 to node location 16. Such extended opening can be described to as a xe2x80x9cself-aligned contact openingxe2x80x9d, referring to the fact that the opening is aligned with sidewall edges of wordlines 20 and 22.
After opening 62 is extended to node location 16, photoresist layer 60 (FIG. 2) can be removed, and subsequent processing utilized for forming bit line contact 46 within opening 62. Also, similar etching described above for formation of bit line contact opening 62 can be utilized to form openings to node locations 14 and 18 for formation of capacitor constructions 36 and 38, respectively, therein. In the shown fabrication process, bit line contact opening 62 is formed prior to forming openings for capacitor constructions 36 to 38. However, other fabrication processes are known wherein openings for the capacitor constructions are formed either before, or simultaneously with, formation of the opening for the bit line contact.
FIG. 3 illustrates an idealized selective etch, wherein the etch stops substantially entirely upon reaching etch stop layer 32. However, as discussed above, prior art etching processes are typically only about two times more selective for sacrificial materials (the material of layer 34) than for protective materials (the material of layer 32). Accordingly, the selective etches do not generally stop substantially entirely upon reaching etch stop layer 32, but rather continue at a slower rate upon reaching layer 32.
FIG. 4 illustrates a prior art problem which can occur as a result of the continued etching of layer 32. Specifically, layer 32 can become thinned to an extent that one or both of sidewalls 28 and 30 are exposed to the etching conditions. Such exposure can lead to etching through the sidewall spacers to expose conductive material 26. In a particularly bad scenario, conductive layer 26 is then shorted to bit line contact 46 when the conductive material of bit line contact 46 is formed within opening 62. Also, the thinning of etch stop layer 32 can lead to unpredictability during a subsequent etch of layer 32 to expose node location 16. Specifically, it is unknown how long to continue a subsequent etch. If the etch continues for too long the etch can undesirably penetrate into substrate 12, and possibly through the diffusion region at node location 16.
For the above-discussed reasons, it is desired to develop alternative methods for selectively etching materials wherein the selectivity of an etch for a given material is improved.
In one aspect, the invention encompasses an etching process. A first material is provided over a substrate. The first material comprises from about 2% to about 20% carbon (by weight). A second material is provided over the first material. The second material is etched at a faster rate than the first material.
In another aspect, the invention encompasses a capacitor forming method. A wordline is formed over a substrate and has a sidewall. An insulative spacer is formed along the sidewall. A node is defined proximate the wordline. An etch stop layer is formed over the wordline and over the insulative spacer. At least one of the etch stop layer and the insulative spacer comprises carbon. An insulative layer is formed over the etch stop layer. The insulative layer is etched to form an opening through the insulative layer and to the etch stop layer. A capacitor construction is formed. The capacitor construction comprises a storage node, dielectric layer and a second electrode. At least a portion of the capacitor construction is within the opening.
In yet another aspect, the invention encompasses a DRAM forming method. A pair of wordlines are formed over a substrate. Three nodes are defined proximate the wordlines. The three nodes comprise a first node, second node and third node. The second node is in gated electrical connection with the first node through one of the wordlines and in gated electrical connection with the third node through the other of the wordlines. An etch stop is formed proximate the wordlines. The etch stop comprises carbon. An insulative layer is formed over the etch stop. A first, second and third opening are formed to extend through the insulative layer. The forming the first second and third openings comprises etching through the insulative layer to the etch stop. A first capacitor construction is formed in electrical connection with the first node, a second capacitor construction is formed in electrical connection with the third node, and a bit line contact is formed in electrical connection with the second node.
In other aspects, the invention includes semiconductive material assemblies, capacitor constructions and DRAM constructions.